摘要
针对FPGA和多DSP系统中各部分所需的复位信号需满足相应的复位时间和正确次序的要求,在介绍了两种传统复位信号产生方法的基础上,提出了一种利用外部器件TPS3307产生原始复位信号,并在FPGA中构建逻辑硬件看门狗,采用异步复位、同步释放的方式复位多DSP的设计方法。给出部分关键设计的源程序,并在一片Xilinx公司的FPGA(XC2V1000)芯片与4片ADI公司的DSP(TS201)组成的系统中进行了验证,结果表明该设计方法能提高系统稳定性和可靠性。
For FPGA and muhi-DSP system, the required reset signal must meet requirements of corresponding reset time and correct order. Based on the introduction of two traditional generating methods of reset signal, this paper presents a new method for resetting muhi-DSP system. By the way of asynchronous resetting and synchronous release, this method uses an external device TPS3307 to produce the original reset signal, and constructs the logic hardware watchdog in FPGA. The original program of key design is given. In the system which is made up of a Xilinx＇s FPGA （XC2V1000） and four ADI＇s DSP （TS201）, this design method is verified successfully. The results prove that the design method can improve system＇s stability and reliability.
出处
《微计算机信息》
2010年第5期31-32,35,共3页
Control & Automation
基金
基金申请人:李亚捷
项目名称:基于FPGA的EPON光线路终端系统的研究
基金颁发部门:湖南省教育厅(09C080)
