摘要
目标航迹滤波算法的实现通常是在PC机上通过软件实现滤波,滤波等待时间为毫秒级,且需要的设备量体积大。为了缩短滤波等待时间,减小设备体积,以工程实现为目标,以经典航迹滤波算法为基础,提出了一种新的算法硬件解决方案。目标航迹滤波由嵌入式DSP实现,再通过FPGA局部总线实时上传。经实践验证该方法实现的目标航迹滤波在系统时钟为40 MHz的情况下,DSP滤波网络等待时间仅为1.475μs。
The flight track filter algorithm is usually implemented through PC, where the latency time of the system reach milliseconds and the volume of the device is bulky. In order to shorten the latency time of the filter and reduce the volume of device, a new scheme is proposed taking the classical flight track filter algorithm as the basis. The flight track filter algorithm of the target is implemented through embedded Digital Signal Processing （DSP） , and is transferred through FPGA local bus in real time. It is proved that in the target flight track filter implemented through the algorithm with the system clock as 40 MHz, the filter-net latency time is only 1. 475μs .
出处
《电光与控制》
北大核心
2010年第4期93-96,共4页
Electronics Optics & Control
关键词
数字信号处理
FPGA
高速α-β滤波
IIR
digital signal processing
FPGA
high-speed α-β filter
Infinite Impulse Response （IIR）
