摘要
本文提出了一种SOC互联总线测试完整性故障的结构优化方法,本方法是在功耗限制下通过分配TAM使测试时间最小,从而优化了系统测试结构。本文先对测试测试集进行二维压缩分割SI测试集成几个SI组初始化测试结构,为每个核分配一位TAM,通过为每个的TAM进行计算后找出关键TAM,再通过在功耗限制下,反复分配空闲TAM给关键TAM和共享TAM的方法进行测试时间的减少。对ITC‘02的试验结果表明,本方法能在功耗限制下大大减少了SOC测试时间。
The paper proposes a new test architecture optimization for the singal integrity faults on the core-External interconnects.The test architecture optimization distributes TAM for all SI groups under power constraint, and makes the test time minimizing.The solution computes test time for each TAM, then designs TAM and optimizes the test architecture by distributing free TAMs and sharing TAMs.The experiments on the ITC＇02 show that our solution could save a lot test time under power constraint.
出处
《微计算机信息》
2010年第8期112-113,116,共3页
Control & Automation
