摘要
介绍了基于Σ-Δ调制技术的小数分频的锁相环是怎样降低输出杂散的。正是因为基于Σ-Δ调制技术的小数分频与传统小数分频相比具有较低的输出杂散,应用前景广阔。通过实例分析说明在设计频率综合器时,采用小数分频替代整数分频,以达到改善相位噪声的目的。为了实现小步进,通常采用DDS+PLL,在对频率转换时间要求不高的情况,也可以用小数分频来替代。
It is introduced how the fractional-N PLL based on Σ-Δ modulation technology decreases output spurs.Fractional-N PLL based on Σ-Δ modulation technology will be applied widely,due to its lower output spurs compared with traditional fractional-N PLL.It is illustrated that integer frequency synthesizer can be replaced by fractional-N PLL,in order to debase phase noise.In case of not strict frequency conversion requirement,the DDS＋PLL which usually can be used to achieve small step,can be replaced by fractional-N PLL.
出处
《无线电工程》
2010年第4期49-51,共3页
Radio Engineering
