摘要
采样保持电路的信号精度和建立速度直接影响到整个流水线型模数转换器的分辨率和转换速率.本文改进了辅助运放的共模反馈结构,解决了传统结构中跨导运放连续时间共模反馈(CMFB)电路设计困难,偏置电路复杂的问题,使用工作在饱和区边沿的MOS管对实现反馈结构,使输出共模电平在1.65 v快速稳定.该采样保持电路基于0.5μm 2P3M CMOS工艺,使ADC达到了10位,40 MHz的性能,一级采样电路在3.3 V的电压下其功耗为6 mW.
Sample-and-hold circuit is in the front of the ADC, the setting error and setting speed are the most important parameters of the Sample - and-hold circuit, which affects the resolution and speed of the whole pipelined ADC directly. To conquer the difficulty of designing in the tradition OTA of CMFB and to debase the complexity in the biasing circuit, we ameliorate the configuration of CMFB of assistant operational amplifier, and use a pair of MOS, which works in the edge of saturation area to form the configuration of feedback. The common-mode voltage is 1.65 V that electrical level is fast and steady. Based on 0. 5 μm 2p3M COMS technology, a sample - and - hold circuit of pipelined ADC is researched and designed. The ADC which based on this sample - and - hold circuit arrive the performance of 10 bit, 40 MHZ. The watt loss is 6mW when the fist sample circuit is under the press of 3.3 V.
出处
《四川大学学报（自然科学版）》
CAS
CSCD
北大核心
2010年第2期311-316,共6页
Journal of Sichuan University(Natural Science Edition)
