摘要
高速下行分组接入(HSDPA)技术是实现提高3G网络高速下行数据传输速率最为重要的技术,F-HARQ为其核心技术。在分析各种混合重传请求技术(HARQ)原理基础上,完成发送端F-HARQ硬件模块的设计及其Verilog实现,并通过FPGA仿真验证,结果表明所设计的硬件模块发送速率达到50MHz。
HSDPA is the hardcore technology of 3G to improve data rate of high-speed downloading.And F-HARQ is one of the core protocol of HSDPA.By analysing the principles and performances of HARQ,hardware module of F-HARQ is designed with Verilog HDL.And then simulated in Quartus II tools and downloaded to the proper FPGA device,proved the validity.
出处
《微计算机信息》
2010年第14期122-123,70,共3页
Control & Automation
