摘要
通过对AES算法S盒构造原理的研究,利用其中仿射变换的系数具有循环移位的周期性特点对电路结构进行改进,提出一种面积优化的AES算法S盒组合逻辑电路设计方法.该方法基于流水线技术,采用倍频复用的电路结构,较传统结构减少了逻辑资源的使用.经过EDA工具综合仿真和实际系统验证,该方法比Wolkerstorfer和Satoh的S盒有限域实现的硬件规模分别缩减了47.53%和41.49%,比Morioka的S盒真值表实现的硬件规模缩减了21.43%.该设计方案已成功用于一种基于FPGA实现的密码专用处理器设计中.
Based on the research on S-box constitution algorithm of Advanced Encryption Standard,we use the periodical characteristic of affine transformation in S-box to improve the circuit architecture and propose an area optimized combinational logic S-box implementation of AES.We multiply the circuit frequency and reuse the circuit with the pipeline technology.The synthesis result shows that the new S-box functional unit not only decreases the area of byte substitution compared with traditional S-box combinational logic by 47.53% and 41.49% and with truth table S-box combinational logic by 21.43%,but also maintains the critical delay of the circuit.Using the unit-gate model approximations,the hardware gate count of S-box is 880 gates.And the S-box scheme is applied to the application specific instruction processor for cryptography which is tested on Altera＇s FPGA Cyclone II EP2C20.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2010年第4期939-942,共4页
Acta Electronica Sinica
基金
国家863高技术研究发展计划重点项目"工业无线技术及网络化测控系统研究与开发"(No.2007AA041201)
关键词
S盒字节替换
仿射变换
组合逻辑
面积优化
S-box subbytes
affine transformation
combinational logic
area optimization
