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热量敏感的众核芯片多播并行测试方法 被引量：3

A Thermal-Aware Parallel Multicast Testing Method Based on Many-Core Chips
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摘要 为了解决芯片测试过程中功耗密度大造成的局部过热(简称"热斑")问题,提出一种热量敏感的多播并行测试方法.对众核芯片采用多播并行测试时面临的"热斑"问题进行分析,提出一种无"热斑"的多播测试路径生成算法;在温度容限内对生成的多条单类同构芯核多播测试路径进行并行优化,形成无"热斑"的快速并行测试方案,同时缩短了测试时间.实验结果表明,采用文中方法能够有效地避免多播并行测试时的"热斑",并使测试时间缩短近45%. The local overheating problem,which is referred to as hotspot,has become an important problem for parallel testing of many-core chips.This paper proposes a thermal-aware parallel multicast testing method to avoid hotspots.Firstly,we analyze the hotspots caused by parallel multicast test of many-core chips.Based on the above analysis,a heuristic algorithm is proposed to avoid hotspots during the generation of one multicast test access path.Finally,for further reducing the test time,we give an optimal solution of selecting candidate multicast test access paths which can coexist under the thermal constraints.Experimental results show that the hotspots can be eliminated,and the test time can be reduced by approximately 45 percent.
作者 方芳 韩银和 李晓维
机构地区 合肥工业大学管理学院 合肥工业大学计算机与信息学院 中国科学院计算机系统结构重点实验室
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2010年第5期845-851,共7页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金重大研究计划(90718037) 国家"八六三"高技术研究发展计划(2007AA01Z113) 博士点基金新教师项目(200803591033) 中国科学院计算机系统结构重点实验室开放课题(ICT-ARCH200704)
关键词 众核芯片 并行测试 多播技术 热斑 many-core chip parallel testing multicast hotspot
分类号 TP306.2 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献13

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二级参考文献11

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共引文献2

同被引文献18

  • 1DeBenedictis E P. Will moore′s law be sufficient[A].Pittsburgh:ACM,2005.45-56.
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  • 3P T Gonciari,B Al-Hashimi. Improving compression ra-tio,area overhead,and test application time for system-on-a-chip test data compression/decompression[A].Paris:ACM,2002.604-611.
  • 4Erik Larsson,Klas Arvidsson. Efficient test solutions for core-based designs[J].{H}IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2004,(05):758-775.
  • 5Krishnendu Chakrabarty. Test scheduling for core-based systems using mixed-integer linear programming[J].{H}IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2000,(10):1163-1174.
  • 6Sandeep Korann. On test scheduling for core-based SoCs[A].Baugalore:ACM,2002.505-510.
  • 7Gang Zeng,Hideo Ito. Concurrent core test for test cost reduc-tion using merged test set and scan tree[A].San Jose:IEEE,2005.143-146.
  • 8M Alexandre,Amory Frederico Ferlini. DfT for the reuse of networks-on-chip as test access mechanism[A].Berkeley:IEEE,2007.435-440.
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  • 10C Liu,V Iyengar,J Shi. Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking[A].Palm Springs:IEEE,2005.349-354.

引证文献3

二级引证文献11

计算机辅助设计与图形学学报
2010年 第5期

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