摘要
为了减少层次型SoC测试时间,实现父核与子核的并行测试,本文设计了一种的测试环单元结构。该测试环单元通过在内部增加一个一位的寄存器,用来满足父核测试对子核的要求,解决层次型SoC中父核与子核并行测试的冲突。利用Verilog HDL进行设计,在QuartusⅡ下通过仿真验证。结果表明此结构安全性得到可靠地保障。
To reduce the test time of hierarchical SoC and complete the parallel test of the parent and child cores,a new wrapper cell structure has been designed in this paper. This wrapper cell solves the conflicts between parent and child cores by adding a 1-bit register in the structure. The structure is designed with Verilog HDL, and simulated with Quartus Ⅱ. The results show that the safety of this structure is reliably ensured.
出处
《国外电子测量技术》
2010年第5期56-59,81,共5页
Foreign Electronic Measurement Technology
