摘要
数字下变频与脉冲压缩一直是雷达信号处理中的关键技术之一。应用现场可编程门阵列(FPGA)的IP核技术,研究了一种基于FPGA的数字下变频与脉冲压缩系统的实时实现方法。首先提出了系统的整体结构,然后介绍了数字下变频模块、脉冲压缩模块及接口模块的设计方法。在单片FPGA上实现了对实际采集的中频Chirp信号进行8K点或2K点可变点数的数字下变频与脉冲压缩处理,通过与Matlab软件计算结果的对比,验证了FPGA实时计算的正确性。最后分析了系统的可实现性与实时性。
Digital down-conversion（DDC） and pulse compression are always the key technologies in radar signal processing. This paper, taking advantage of the FPGA IP core technology, introduces a way of real-time implementation of digital down-conversion and pulse compression system based on FPGA. The structure of system is first proposed, and then the designs of DDC, pulse compression module and the interface module are introduced. The IF（Intermediate Frequency） sampled 8K or 2K point Chirp signal is pro cessed by the system on a single FPGA chip. The result processed by the FPGA is compared with that calcu lated by Matlab software. The system has been proved to be real time and feasible.
出处
《雷达科学与技术》
2010年第2期133-138,145,共7页
Radar Science and Technology
关键词
雷达
数字下变频
脉冲压缩
现场可编程门阵列
radar
digital down-conversion
pulse compression
field programmable gate array（FPGA）
