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基于FPGA的新型数字锁相倍频方法 被引量:6

New Method of Digital Phase-locked Frequency Based on FPGA
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摘要 为了克服模拟锁相倍频电路在应用过程中易受温度和电压影响、锁相时间长、存在直流零点漂移及部件饱和等缺欠,以实现对被测信号的高速高精度采样,提出了一种基于FPGA的新型数字锁相倍频方法。该方法依据锁相倍频的基本原理,通过检测被测信号的边缘计算出频率值,找到相应的指针位置,再根据产生的分频因子来控制数控振荡器的输出信号,从而完成对被采集信号的锁相倍频。经过仿真分析,验证了该方法的可行性,证明了其具有精度高、锁相速度快等优点。 In order to overcome the shortcomings of the analog phase-lock frequency multiplication circuit,including the effects of the temperature and voltage in the application process,long-time phase-locked,zero drift in DC and parts saturated,a new type of FPGA,based on the digital phase-locked frequency-multiplication method was proposed.This method can achieve high-speed,high-precision in the process of sampling measured signals.According to the basic principles of phase-locked frequency multiplication,it could calculate the frequency value by detecting the edge of measured signal,and then find the location of the corresponding pointer,after that control the digital-controlled oscillator's output signal with the generated the sub-frequency factor,complete the phase-locked multiplication of the collected signal.Through the simulation analysis,this method can be verified its feasibility and be proved its high accuracy,the advantages of phase-locked speed.
出处 《仪表技术与传感器》 CSCD 北大核心 2010年第5期60-62,共3页 Instrument Technique and Sensor
基金 辽宁省自然科学基金资助项目(20062043) 辽宁省科技攻关资助项目(2006219005) 辽宁省教育厅科研资助项目(200060629) 沈阳市科技局科技支撑计划支持项目(1081229-1-00)
关键词 锁相 倍频 现场可编程门阵列 小数分频 边缘检测 phase-locked frequency-multiplier FPGA decimal divider edge detection
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