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A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors

A process simplification scheme for fabricating CMOS polycrystalline-Si thin film transistors
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摘要 A process simplification scheme for fabricating CMOS poly-Si thin-film transistors(TFTs) has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer(LAITS).By this LATITS scheme,a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus(or boron) dopant through the spacer,and then the n~+-source/drain(n~+-S/D)(or p~+-S/D) region is formed via using the same photo-mask layer during CMOS integration.For both n-TFT and p-TFT devices,as compared to the sample with conventional single n~+-S/D(or p~+-S/D) structure,the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field.In addition,the resultant on-state currents only show slight degradation for the LATITS scheme.As a result,by the LATITS scheme,CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration. A process simplification scheme for fabricating CMOS poly-Si thin-film transistors(TFTs) has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer(LAITS).By this LATITS scheme,a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus(or boron) dopant through the spacer,and then the n~+-source/drain(n~+-S/D)(or p~+-S/D) region is formed via using the same photo-mask layer during CMOS integration.For both n-TFT and p-TFT devices,as compared to the sample with conventional single n~+-S/D(or p~+-S/D) structure,the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field.In addition,the resultant on-state currents only show slight degradation for the LATITS scheme.As a result,by the LATITS scheme,CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第6期39-43,共5页 半导体学报(英文版)
基金 Project supported by the National Science Council(NSC),Taiwan,China(No.NSC 97-2221-E-011-136).
关键词 polycrystalline-Si thin-film transistor process simplification large-angle-tilt-implantation polycrystalline-Si thin-film transistor process simplification large-angle-tilt-implantation
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