摘要
该文设计了一种适用于IEEE802.1AE协议的GCM高速硬件结构。GCM的核心模块包括AES和Ghash两部分。该文中Ghash模块采用了一种新型的并行乘加器,可以同时处理多组数据,而不需要预先确定等待处理的分组数据总数;为了支持密钥每个时钟周期不断变化,AES中密钥扩展模块采用了循环展开结构。该文采用二度并行的Ghash模块实现了GCM高速加密电路,使用Fujitsu 0.13μm 1.2V 1P8M CMOS工艺进行逻辑综合,得到吞吐率为97.9Gbps,面积为547k门,时钟频率达到764.5MHz。
This paper presents a high-speed GCM architecture,which is suitable for IEEE 802.1AE protocol.The core modules of GCM include AES and Ghash.In Ghash module,a new parallel multiply-adder is proposed,which can handle several sets of data at the same time without knowing the total number of data blocks in advance.To support constant key changes in each clock cycle,loop-unrolling structure is used in KeyExpansion module of AES.A GCM encryptor design example with 2-parallel Ghash is implemented and the performance is evaluated by utilizing Fujitsu 0.13 μm 1.2 V 1P8M CMOS technology and a very high throughput of 97.9 Gbps is obtained with 547 Kgates,operating at 764.5 MHz.
出处
《电子与信息学报》
EI
CSCD
北大核心
2010年第6期1515-1519,共5页
Journal of Electronics & Information Technology
基金
国家863计划项目(2008AA01Z135)
国家自然科学基金(60876017)资助课题
