期刊文献+

基于ARINC 659的FPGA原型验证平台的构建与实现 被引量:6

Design of FPGA prototype verification platform for ARINC 659
下载PDF
导出
摘要 依据ARINC 659协议的芯片设计中复杂功能逻辑的验证需求,提出了一款用于验证ARINC 659芯片逻辑功能的FPGA验证平台,全面论述了ARINC 659验证平台的构建以及ARINC 659芯片FPGA原型验证的全过程。实验结果表明,该验证平台能较为充分、全面地验证ARINC 659芯片的逻辑功能,提高了验证效率,缩短了芯片开发中的验证周期。 A design of FPGA verification platform for verification of logical function of ARINC 659 chip is presented,which is based on the verification requirement of complex function logic in the ARINC 659 chip design.The design of ARINC 659 verification platform and the whole process of ARINC 659 chip FPGA prototype verification are discussed.The verification result indicates this verification platform can sufficiently and fully validate the logical function of ARINC 659 chip,improve the efficient of verification,abbreviate the verification period in chip exploiture.
出处 《计算机工程与设计》 CSCD 北大核心 2010年第12期2726-2728,2732,共4页 Computer Engineering and Design
基金 微电子预研专项基金项目(513080105101) 微电子预研重点基金项目(9140A160107061) 陕西省2007年度自然科学基础研究计划基金项目(2007F21)
关键词 总线协议芯片 现场可编程门阵列 验证平台 实时操作系统 ARINC659芯片 bus protocol chip FPGA verification platform RTOS ARINC 659 chip
  • 相关文献

参考文献7

二级参考文献29

  • 1冯福来.容错计算系统的特性,性能/可靠性量度及其评价[J].航空与航天,1993(3):47-52. 被引量:2
  • 2马凤翔,孙义和.SoC原型验证技术的研究[J].电子技术应用,2005,31(3):70-73. 被引量:5
  • 3李济世,王鹏,金德鹏,曾烈光.MSTP芯片的软硬件协同验证平台设计[J].光通信技术,2005,29(11):4-6. 被引量:7
  • 4国家军用标准.GJB5186-2003,数字式时分指令/响应型多路传输数据总线测试方法[s].2003.
  • 5Prakash Rashinkar, Peter Paterson. System on a Chip Verification: Methodology and Techniques [ M ]. Kluwer Academic Publishers ,2001.
  • 6Furber S[英],著,田泽,于敦山,盛世敏,译.ARMSoC体系结构[M].北京:北京航空航天大学出版社,2002.
  • 7ARINC SPECIFICATION 659 BACKPLANE DATA BUS [ A]. the Airlines Electronic Engineering Committee [ C ]. DEC. 27,1993.
  • 8Bruce K. Walker, Norman M. Wereley, Effects of Redundancy Management on Reliability Modeling [ J ]. IEEE Trans. Reliaility, 1989,38 (4).
  • 9Shem- Tov Levi and Ashok K. Agrawada, Fault Tolerant System Design[ Z]. 1995.
  • 10B Buth, M Kouvaras,J Peleska, et al. Deadlock Analysis for a Fault_Tolerant System [ A ]. In Proceedings of the AMAST Conference [ C ]. November 1997, Springer LNCS ( 1997 ).

共引文献47

同被引文献46

  • 1王世好,王歆民,刘明业.嵌入式系统软硬件协同验证中软件验证方法[J].计算机研究与发展,2005,42(3):514-519. 被引量:10
  • 2李济世,王鹏,金德鹏,曾烈光.MSTP芯片的软硬件协同验证平台设计[J].光通信技术,2005,29(11):4-6. 被引量:7
  • 3刘慕涛,张磊,王艳,周晓中,张红雷,左芸.基于XML的API自动化测试工具设计与实现[J].计算机工程,2007,33(13):96-98. 被引量:13
  • 4Balakrishnan R V. IEEE 896 Futurebus--A Solution to the Bus Driving Problem[M ]//National Semiconductor Inter- face Data Book. [ s. l. ] : [ s. n. ], 1988.
  • 5Borrill P. Futurebus : the Ultimate in Advanced System Buses [C]//Proc. Buscon' 86 West. [s.l. ] :[s. n. ] ,1986:210- 216.
  • 6IEEE 1194. l--Electrical Characteristics of Backplane Transceiver Logic BTL Interface Circuits[ S ]. 1990.
  • 7IEEE 896.2-Futurebus+ Physical Layer and Profile Specifications [S ]. 1992.
  • 8Martinez J, Kempainen S. Futurebus + Wired-OR Glitch Effects and Filter [ M ]//National Semiconductor High Per- formance Bus Interface Designer' s Guide. [s. l. ] : [ s. n. ], 1991.
  • 9Aichinger B P. Futurebus+ as an I/O Bus, Profile B[C] ,// Proc . of 19th int Symp. on Computer Architecture. [ s. l. ] :[ s. n. ], 1992:300-307.
  • 10Gustavson B B, Theus J. Wire-OR Logic on Transmission Lines[J]. IEEE Micro. ,1983,3(3) :51-55.

引证文献6

二级引证文献11

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部