摘要
设计了一个地址有效时间为５ｎｓ的３２ｋｂ（２ｋ×１６位）ＣＭＯＳ静态随机存储器。设计中采用优化的阵列结构、分段字线译码，以达到１．７５ｍＷ／ＭＨｚ的低功耗；采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲，以提高存储器的读写频率。同时，利用两级敏感放大器的层次式结构降低数据线的电压幅度，进一步降低了功耗。
A 32 kb(2 k×16) CMOS SRAM with 5 ns access time is presented. The SRAM, having a cell size of 8.2 μm × 13.6 μm and a chip size of 2.54 mm × 5.64 mm , is fabricated by using 0.6 μm N well single poly and double metal CMOS technology. A low power dissipation of 1.75 mW /MHz is achieved by using an optimized array architecture and a devided word line decoder. A fast access time is obtained by utilizing a bit line equalizing technique, a high speed hierarchical sense amplifier and a preset data output buffer. In addition, the sense amplifier’s hierarchical architecture can be used to reduce the data bus voltage amplitude, which further reduces the power dissipation.
出处
《微电子学》
CAS
CSCD
北大核心
1999年第2期83-88,共6页
Microelectronics
关键词
静态随机存储器
地址有效时间
阵列结构
SRAM,Address access time, Sense amplifier, CMOS EEACC 1265D, 2570Keywords SRAM,Address access time, Sense amplifier, CMOS EEACC 1265D, 2570〖ST
