摘要
提供了一种全新的高性能异步FIFO设计方案.首先定义了FIFO的通信协议和总体结构设计,然后围绕如何提高FIFO性能依次论述了存储阵列设计、读写控制逻辑和空/满判断逻辑的设计方法.通过与FPGA本身的FIFO模块比较,该方案可以提高FIFO性能30%以上.
This paper presents a high performance FIFO design that interfaces subsystems on a chip working at different speeds. The communication protocol and the architecture of FIFO are proposed at first. Aim at improving its operation speed, the design of storage array, read/write control logic and full/empty status logic are described specifically. Compared with the existing FIFO block, the design’s performance improvement ratio is more than 30 percent.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第8期145-148,共4页
Microelectronics & Computer
关键词
异步FIFO
亚稳态
多时钟
asynchronous FIFO
meta-stability
multiple clock
