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应用段固定折叠计数器的低功耗测试方案

Low Power Test Scheme Based on Segment Fixing Folding Counter
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摘要 提出了一种低功耗的测试模式生成方法,采用段固定折叠计数器将确定的测试立方集嵌入片上生成的测试模式序列中.该测试模式生成器需要依赖随机访问扫描体系结构,测试时新的测试模式可直接载入扫描单元而不需要经过扫描移位.基于ISCAS-89基准电路的实验表明,该文提出的方案可以有效降低测试数据量、测试应用时间和测试功耗. A test pattern generation method for low power test is proposed.The deterministic set of test cubes is embedded into the test pattern sequences generated with a segment fixing folding counter.This test pattern generator relies on the random access scan（RAS） architecture.In RAS,a new test pattern is directly loaded into scan cells without a shift procedure.Experimental results on ISCAS-89 benchmark circuits demonstrate that this scheme can reduce data volume,application time and power consumption of the test simultaneously.
作者 陈田 梁华国 张敏生 王伟 易茂祥
机构地区 合肥工业大学计算机与信息学院 中国科学院计算技术研究所
出处 《应用科学学报》 EI CAS CSCD 北大核心 2010年第4期399-405,共7页 Journal of Applied Sciences
基金 国家自然科学基金(No.60876028,No.60633060) 国家“863”高技术研究发展计划基金(No.007AA01Z113-1) 博士点基金(No.200803590006) 安徽省高校省级自然科学研究重点项目基金(No.KJ2010A280)资助
关键词 段固定 随机访问扫描 数据压缩 低功耗 segment fixing random access scan data compression low power
分类号 TP391.72 [自动化与计算机技术—计算机应用技术]
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参考文献10

  • 1LIANG Huaguo,HELLEBRAND S,WUNDERLICH H J.Two-dimensional test data compression for scanbased deterministic BIST[C] //Proceedings of IEEE International Test Conference.Baltimore,MD,2001:894-902.
  • 2CHAKRABARTY K,MURRAY B T,IYENGAR V.Builtin test pattern generation for high-performance circuits using twisted-ring counters[C] //Proceedings of IEEE VLSI Test Symposium.San Diego,USA,1999:22-27.
  • 3ZORIAN Y.A distributed BIST control scheme for complex VLSI devices[C] //Proceedings of IEEE VLSI Test Symposium.1993:4-9.
  • 4BAIK D H,KAJIHARA S,SALUJA K K.Random access scan:a solution to test power,test data volume and test time[C] //Proceedings of International Conference on VLSI Design.Mumbai,India,2004:883-888.
  • 5MUDLAPUR A S,AGRAWAL V D,SINGH A D.A random access scan architecture to reduce hardware overhead[C] //Proceeding of International Test Conference,2005:350-358.
  • 6HU Yu,LI Xiaowei,LI Huawei,WEN Xiaoqing.Compression/scan co-design for reducing test data volume,scan-in power dissipation and test application time[C] //Proceedings of Pacific Rim International Symposium on Dependable Computing,Changsha,China,2005:175-182.
  • 7FUJIWARA H,YAMAMOTO A.Parity-scan design to reduce the cost of test application[J].IEEE Transaction on Computer-Aided Design of Circuits and Systems,1993,12(10):1604-1611.
  • 8WANG S.A BIST TPG for low power dissipation and high fault coverage[J].IEEE Transactions on Very Large Scale Integration,2007,15(7):777-789.
  • 9BAIK D H,SALUJA K K.Progressive random access scan:a simultaneous solution to test power,test data volume and test time[C] //Proceedings of IEEE International Test Conference,2005(11):359-368.
  • 10梁华国,蒋翠云.使用双重种子压缩的混合模式自测试[J].计算机研究与发展,2004,41(1):214-220. 被引量：38

二级参考文献20

  • 1[1]M Abramovici, M Breuer, A Friedman. Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990
  • 2[2]K-T Chen, C-J Lin. Timing driven test point insertion for full-scan and partial-scan BIST. The IEEE Int'l Test Conf, Washington, D C, 1995
  • 3[3]Y Savaria, M Yousef, B Kaminska .et al.. Automatic test point insertion for pseudo-random testing. The Int'l Symp on Circuits and Systems, 1991. http://ieeexplore.ieee.org/Xplore/DynWel.jsp
  • 4[4]M J Y Williams, J B Angell. Enhancing testability of large-scale integrated circuits via test points and additional logic. IEEE Trans on Computers, 1973, C-22(1): 46～60
  • 5[5]K Chakrabarty, B T Murray, V Iyengar. Built-in test pattern generation for high-performance circuits using twisted-ring counters. The 17th IEEE VLSI Test Symp, Dana Point, CA, 1999
  • 6[6]K Chakrabarty, S Swaminathan. Built-in self testing of high-performance circuits using twisted-ring counters. The 2000 IEEE Int'l Symp on Circuits and Systems, 2000. http://ieeexplore.ieee.org/Xplore/DynWel.jsp
  • 7[7]C Dufaza, G Cambon. LFSR based deterministic and pseudo-random test pattern generator structures. European Test Conference, Munich, 1991
  • 8[8]S Hellebrand, J Rajski, S Tarnick .et al.. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers. IEEE Trans on Computers, 1995, 44(2): 223～233
  • 9[9]S Hellebrand, B Reeb, S Tarnick .et al.. Pattern generation for a deterministic BIST scheme. IEEE/ACM Int'l Conf on CAD-95, San Jose, CA, 1995
  • 10[10]S Hellebrand, H-J Wunderlich, A Hertwig. Mixed-mode BIST using embedded processors. Journal of Electronic Testing Theory and Applications (JETTA), 1998, 12(1/2): 127～138

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应用科学学报
2010年 第4期

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