摘要
设计一个实时图像放大引擎IP(Intellectual Property)核,该IP核以最小化硬件资源占用和最短的时钟周期消耗,快速实现预定比例的图像放大。用VHDL(Very-High-Speed Integrated Circuit Hardware Description Language)语言描述,可结合到各种显示输出集成电路芯片中。提出一种简化的D1到XGA(Extended Graph-ics Array)格式转换的有效算法;在此基础上给出算法基于FPGA(Field Programmable Gate Array)上的实现形式和流水线处理结构。实验表明,该设计的图像放大系统可实现在65帧/s的显示速率下高质量的D1到XGA格式转换,同时很好地保留图像的边缘信息。
The real-time image to enlarge engine IP（Intellectual Property）core is designed,to minimize the hardware resources of their occupation and the shortest clock cycle consumption,and to achieve the ratio of the image to enlarge.The IP core using VHDL（Very-High-Speed Integrated Circuit Hardware Description Language）language description can be integrated into a variety of display output integrated circuit chip.A simplified format D1 to XGA（Extended Graphics Array）effective method is proposed.An algorithm based on FPGA（Field Programmable Gate Array）,and the form and pipeline processing structure are also given.Experiments show that the design of image magnification system can display per second rate 65 high-quality D1 to XGA format,the same time keep a good image edge information.
出处
《吉林大学学报（信息科学版）》
CAS
2010年第4期410-413,共4页
Journal of Jilin University（Information Science Edition）
基金
国家自然科学基金资助项目(60372058
60772101)
关键词
现场可编程门阵列
图像放大
线性插值
扩展图形阵列
field programmable gate array（FPGA）
image magnification
liner interpolation
extended graphics array（XGA）
