摘要
采用0.5μm CMOS集成电路工艺,设计出一种应用于电容式加速度计中的新型低失调、低功耗放大器。分析了放大器对加速度计系统性能的影响,给出原有放大器的不足之处。新型放大器由三级组成,第一级与第二级是标准的差分输入单端输出放大器,第三级为class-A输出级。采用共源共栅的两级高增益差分级提高了CMRR及静态失调,再通过版图技术减小动态失调,使得整体失调下降。恰当的选择差分输入管的沟道长度会得到输入参考噪声最小值。测试结果表明,放大器输入失调电压温漂为0.78μV/℃,等效输入噪声20.05nV/Hz,加速度计噪声仅为8μg/Hz,其全温区零点变化量0.5mV/℃。
In this paper, design and characterization of a new low - offset, low - power amplifier which is used in capacitive accelerometer in 0. 5μm CMOS process is presented. Analyzes the accelerometer amplifier system performance and found shortcomings of the original amplifier. The new amplifier comprises three gain stages. The first stage and the second stage are standard differential amplifier stages whereas the third stage is a class - A output stage. This is based on cascading two high - gain differential stages to form a composite front - end gain stage for enhancing CMRR as well as reducing systematic errors, and incorporating an averaging layout technique to reduce the random mismatch errors. By choosing the optimum value for the channel length of the differential input pair the input - referred 1/f noise will be minimized. Test results show that the offset drift and the equivalent input noise of new amplifier respectively is 0. 78μV/℃ and 20.05nV/√Hz, the noise accelerometer is 8μg√Hz and the whole temperature range the variation is 0.5mV/℃.
出处
《微处理机》
2010年第4期22-25,共4页
Microprocessors
