摘要
提出了一种低功耗的混合谐振时钟分布机制,通过改进的旋转行波振荡器产生和分布方波形全局时钟信号,采用基于片上变压器的谐振电路产生局部谐振时钟信号.在SMIC0.13μm CMOS工艺下,对目标频率为1.91GHz的混合时钟网络进行了设计和仿真,能够显著降低时钟系统功耗.
This paper proposes a hybrid resonant clocking distribution scheme.The global square-wave clock signal is produced and distributed by an improved rotary traveling wave oscillator.And the local resonant clock signal is generated by a transformer based resonant circuit.The hybrid clocking network with target frequency of 1.91GHz is designed and analyzed through SPICE under SMIC 0.13μm CMOS technology,which can reduced power consumption significantly in the clocking system.
出处
《微电子学与计算机》
CSCD
北大核心
2010年第10期87-90,95,共5页
Microelectronics & Computer
基金
国家重点基础研究发展规划项目(2009ZX01034-001-001-006)
国家自然科学基金项目(60906014)
关键词
谐振时钟
时钟分布网络
旋转行波振荡器
片上变压器
resonant clock
clock distribution network
rotary traveling wave oscillater
on-chip transformer
