摘要
ARINC659总线与机载计算机PCI9054接口设计中因工作时钟不同而出现亚稳态现象。为此,描述亚稳态机理,给出降低亚稳态产生条件,提出采用同步器实现控制信号传递和格雷码+异步FIFO实现数据传输。结合PCI9054接口信号时序,设计总线接口模块,通过Verilog编码实现进行仿真实验。结果表明,异步FIFO解决了ARINC659与PCI9054之间的跨时钟数据传输。
Metastability emerges from designing the interface between ARINC659 and PCI9054 because of the two different clocks.This paper describes the mechanism of the metastability,gives conditions for reducing metastable produce,and proposes achieving control signal transmission by synchronizer and data transfer by Gray code ＋ FIFO.With PCI9054 interface signal timing,the paper designs the bus interface module,and implements the interface design with the Verilog language.Result shows that asynchronization FIFO solves cross-clock data transfer between ARINC659 and PCI9054.
出处
《计算机工程》
CAS
CSCD
北大核心
2010年第20期214-216,共3页
Computer Engineering
