摘要
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
A 512-bit EEPROM IP was designed by using just logic process based devices. To limit the voltages of the devices within 5.5 V, EEPROM core circuits, control gate （CG） and tunnel gate （TG） driving circuits, DC-DC converters： positive pumping voltage （Vpp=4.75 V）, negative pumping voltage （VNN=-4.75 V）, and VNNL（= VNN/2） generation circuit were proposed. In addition, switching powers CG high voltage （CG HV）, CG low voltage （CG_LV）, TG high voltage （TG_HV）, TG low voltage （TG_LV）, VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit. Furthermore, a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed. To reduce a power consumption of EEPROM in the write mode, the reference voltages VREF_VPP for Vpp and VREE_VNN for VNN were used by dividing VDD （1.2 V） supply voltage supplied from the analog block in stead of removing the reference voltage generators. A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed. The result shows that the power dissipation is 0.34 μW in the read mode, 13.76 μW in the program mode, and 13.66 μW in the erase mode.
基金
Project supported by the Second Stage of Brain Korea 21
