摘要
针对使用硬件描述语言进行设计存在的问题,提出一种基于FPGA并采用DSP Builder作为设计工具的数字信号处理器设计方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ设计流程,设计了一个12阶FIR低通数字滤波器,通过Quartus时序仿真及嵌入式逻辑分析仪SignalTapⅡ硬件测试对设计进行了验证。结果表明,所设计的FIR滤波器功能正确,性能良好。
Aiming at the problems in designing DSP using HDL,a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/Quartus Ⅱ, and the design was verified by the timing simulation based on Quartus Ⅱ and practical test based on SignalTap Ⅱ. The result shows the designed filter is correct in function and good in performance.
出处
《电子设计工程》
2010年第11期128-130,共3页
Electronic Design Engineering
基金
渭南师范学院重点科研计划资助项目(09YKF005)
