摘要
设计了一个14位40 MHz、100 dB SFDR、1.8 V电源电压的流水线A/D转换器(ADC)。采用增益自举密勒补偿两级运放,可在保证2Vp-p差分输出信号摆幅的前提下获得130dB的增益,有效地减小了运放有限增益的影响;同时,采用冗余位编码技术和动态比较器,降低了比较器失调电压的设计难度和功耗。该设计采用UMC 0.18μm CMOS工艺,芯片面积为2mm×4 mm。仿真结果为:输入满幅单频9 MHz的正弦信号,可以达到100 dB SFDR和83.8 dBSNDR。
A 14-bit 40 MS/s pipelined A/D converter（ADC）featuring 100 dB SFDR and 1.8 V single power supply was designed.In this circuit,a gain-boosting Miller OTA was used to achieve 130 dB open-loop gain,while maintaining 2 Vp-p differential signal swing,which degraded the OTA finite-gain error effectively.The use of redundancy coding technique and dynamic comparator made the design of comparator easier and also reduced its power consumption.Fabricated in UMC＇s 0.18 μm CMOS technology,the circuit occupies a chip area of 2 mm ×4 mm.Simulation result showed that the circuit achieved an SNDR of 83.8 dB and an SFDR of 100 dB at a full-range single-frequency sine input of 9 MHz.
出处
《微电子学》
CAS
CSCD
北大核心
2010年第6期765-769,773,共6页
Microelectronics
基金
国家高技术研究发展(863)计划基金资助项目"极低功耗系统芯片设计关键技术及应用"(2008AA010700)
