摘要
针对高速模/数转换器件采用单片机控制存在的问题,结合AD7685的工作原理,采用FPGA控制A/D转换器工作,利用Verilog HDL硬件描述语言采用自顶向下的开发模式设计了AD7685采样控制器,并调用FPGA内部逻辑资源搭建而成的FIFO做为缓存。文中介绍了如何生成FIFO宏模块及其调用方法,同时给出了部分程序代码及采样控制电路在QuartusII软件下的仿真结果,并通过Alter公司的FPGA器件EP1C6Q144C8和GW48 EDA教学试验系统来实现A/D采集控制器。实践证明设计的电路能够稳定、可靠的工作。本设计可用于高速应用领域和实时监控及数据采集等方面。
In this paper,contrary to high-speed A/D conversion device is available in single-chip control problems,and according to the principle of AD7685,adopts FPGA to control the use of A/D converter work and calls the internal FPGA logic resources of the FIFO structure which is used as buffer.The article describes how to generate macro FIFO module and call the method.At the same time gives some sample code and the circuit＇s function simulation waveform on Quartus II6.0 is given,and at last the circuit is implemented by configuring the Alter FPGA device EP1C6Q144C8 and GW48 EDA system for teaching and experiments.AD7685 sampling controller is proved to be stable and reliable.The design can be used for high-speed applications and real-time control and data acquisition etc.
出处
《自动化技术与应用》
2011年第1期89-92,共4页
Techniques of Automation and Applications
