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自定义指令集处理器及其工具链设计 被引量：2

Design of a Custom Instruction Set Processor and its Tool Chain
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摘要 针对一种可重构通信基带处理平台提出自定义的处理器指令集,对该指令集进行了编译器的移植和汇编器、连接器的设计,为该平台中的处理器建立了一套开发工具链,并进行了一系列测试.测试结果表明,本文提出的处理器指令集完全能够满足系统要求,建立的工具链能够生成高效的可执行代码. Proposed a processor with custom instruction set for a reconfigurable baseband processing platform. A complete software tool chain is set up, including the porting of C compiler and standard library, the design of assembler and linker, and corresponding tests. Test results show the proposed instruction set and the software tool-chain can meet the requirements of the whole platform and generate efficient code.
作者 杨庆庆 周晓方 杨鸿
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《小型微型计算机系统》 CSCD 北大核心 2011年第2期333-338,共6页 Journal of Chinese Computer Systems
基金 国家自然科学基金项目(60876016)资助 专用集成电路与系统国家重点实验室基金项目(ZD20080103)资助
关键词 自定义指令集 处理器 编译器 LCC custom instruction set processor compiler LCC
分类号 TP333 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献10

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共引文献16

同被引文献12

  • 1周志雄,何虎,杨旭,张延军,孙义和.ASIP处理器的可重定位编译器的设计[J].微电子学与计算机,2007,24(1):38-41. 被引量：2
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  • 3Naessens F,Derudder V,Cappelle H. A 10.37 mm 2 675 mW Reconfigurable LDPC and Turbo Encoder and Decoder for 802.11n, 802.16e and 3GPP-LTE[A].Honolulu,USA:IEEE Press,2010.213-214.
  • 4Purushotham M,Rachid A,Amer B. A Flexible High Th-roughput Multi-ASIP Architecture for LDPC and Turbo Decoding[A].Grenoble,France:IEEE Press,2011.1-6.
  • 5Condo C,Martina M,Masera G. VLSI Implementation of a Multi-mode Turbo/LDPC Decoder Architecture[J].IEEE Transactions on Circuits and Systems I:Regular Papers,2013,(06):1441-1454.
  • 6Sani A H,Coussy P,Chavet C. A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders:A Polynomial Time Mapping Algorithm[J].IEEE Transactions on Signal Processing,2013,(06):4127-4140.
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小型微型计算机系统
2011年 第2期

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