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一种低复杂度GPS载波跟踪环路设计 被引量:13

A Low Complexity Design of GPS Carrier Tracking Loop
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摘要 GPS接收机载波跟踪环路的鉴别器和滤波器设计决定了跟踪环路的性能,也在很大程度上决定了GPS接收机的性能.本文在分析了传统锁相环和锁频环鉴别器算法的基础上,提出了一种锁相锁频环共用四象限反正切函数单元的鉴别器算法;同时,在研究了基于双线性Z变换积分器与矩形波数字积分器的滤波算法基础上,提出了一种基于矩形波数字积分器的锁频环辅助锁相环的滤波器算法.综合这两种新算法给出一种低复杂度的GPS接收机锁相锁频环设计方法.通过理论分析与仿真实验,证实该GPS载波跟踪环路设计不但具有良好的跟踪性能,且与传统设计方案相比具有运算量小,复杂度低,占用资源少等优点,更易于工程实现. A discriminator algorithm and a loop filter structure critically affect the performance of a GPS carrier tracking loop and a receiver.Firstly,from the analysis of the traditional PLL(phase-locked loop) and FLL(frequency-locked loop) discriminators,a new discriminator algorithm is put forward based on a shared four-quadrant arctangent function between PLL and FLL.Secondly,a loop filter design is given based on the boxcar digital integrator by comparison with a digital bilinear transform integrator.Finally,a low complexity design scheme for GPS carrier tracking loop is represented,which is composed of the proposed discriminator and the loop filtering algorithms.The theoretical analysis and simulation results confirm that this novel design has low complexity,less resources and achieves good tracking performance.
出处 《电子学报》 EI CAS CSCD 北大核心 2010年第12期2822-2826,共5页 Acta Electronica Sinica
基金 国家863高技术研究发展计划(No.2009AA12Z312) 国家自然科学基金(No.60972091)
关键词 载波跟踪环路 锁相环 锁频环 环路滤波器 低复杂度 carrier tracking loop PLL(phase-locked loop) FLL(frequency-locked loop) loop filter low complexity
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参考文献10

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二级参考文献46

共引文献80

同被引文献87

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