摘要
基于提高速度和减少面积的理念,对传统的FIR数字滤波器进行改良。考虑到FPGA的实现特点,研究并设计了采用Radix-2的Booth算法乘法器以及结合了CSA加法器和树型结构的快速加法器,并成功应用于FIR数字滤波器的设计中。滤波器的系数由Matlab设计产生。仿真和综合结果表明,Booth算法乘法器和CSA算法加法器树,在满足FIR数字滤波器的性能要求的同时,在电路实现面积上、尤其是速度上有明显的优化;并且当数据量越多时,优化也越明显。
The traditional FIR digital filter was modified with the concept of increasing the speed and reducing the area. Taking into account of the characteristics of FPGA, the Booth Radix-2 algorithm multiplier and the fast adder were designed in the combination with CSA adder and a tree structure, and then the adder and multiplier were used successfully in the design of FIR digital filter. The coefficients of the filter were generated by Matlab. Simulation and synthesis results show that Booth algorithm multiplier and adder tree based on CSA algorithm not only meet the performance requirements of FIR digital filter but also optimize the area on the circuit and especially the speed, and the optimization is more evident when there are a large amount of data.
出处
《现代电子技术》
2011年第6期151-153,共3页
Modern Electronics Technique
基金
福建省科技厅重点项目(2008I0019)
福建省自然基金项目(2009J01285)
福州市科技项目(2010-G-102)
