摘要
保护方式下的异常与中断管理是微处理器设计的重要组成部分．文中探讨了异常与中断的数据结构、定义、表，给出了保护方式下的异常与中断管理算法；提出了异常／中断管理单元（ＥＩＭＵ）的细胞群结构，并指出细胞是异常／中断管理单元的基本测试单位；系统评价了任务门，中断门／陷阱门区别及优缺点．最后用ＥＤＡ 工具ＭＥＮＴＯＲ ＧＲＡＰＨＩＣＳ对异常与中断管理单元及其算法的ＲＴＬ级ＶＨＤＬ描述进行综合与仿真。
After definition and data structure in exception/interrupt management are analyzed, an algorithm is given to deal with the exception/interrupt.In the algorithm there are two mechanisms to answer exception/interrupt: one is to utilize a trap/interrupt gate in current task, the other is to utilize a task gate in another task. As a results, exception or interrupt which can not be processed in current task may use task gate to handle in another task. On the other hand, a basic test unit cell is deduced to generate Boolean value for cell test to control branch in the microprogram. With cell extracted from the algorithm, a kind of cell group structure is put forward to establish exception/interrupt management unit (EIMU). The VHDL RTL description for EIMU and the algorithm is synthesized and simulated in MENTOR GRAPHICS and its simulation proves its validity.
出处
《计算机研究与发展》
EI
CSCD
北大核心
1999年第11期1342-1348,共7页
Journal of Computer Research and Development
关键词
微处理器
NCS
异常
中断
存储器
嵌入式
exception/interrupt management unit (EIMU), interrupt gate, trap gate, task gate, cell
