摘要
随着绝缘体上硅(SOI)技术的快速进展,SOI集成电路的静电放电(ESD)保护已成为一个主要的可靠性问题.研究了基于PD SOI工艺的栅耦合N型金属氧化物半导体管(GCNMOS)电源箝位保护电路,以形成全芯片ESD保护网络.利用HSPICE仿真的方法,可以准确地确定R值和C值,以确定合理的触发电压.根据PD SOI工艺特点设计了基于不同体偏置类型、不同源漏注入类型和不同栅宽的NMOS管的各种GCNMOS电源箝位保护电路,并进行了MPW流片及TLP测试分析,得到源漏深注、体悬浮的H型栅NMOS组成的GCN MOS电源箝位保护电路的抗ESD能力最好,单位宽度(1μm)抗HBM ESD能力可达9.25 V.
With the quick development of silicon-on-insulator（SOI） technology,electro static dischargs（ESD） protection of SOI integrated circuit is becoming a major reliability issue.In order to form whole-chip ESD protection network,this paper investigates the gate coupled N metal oxide semiconductor（GCNMOS） power clamp protection circuit based on partially depleted（PD） SOI technology.The values of resistance and capacitance can be accurately determined by HSPICE simulation method so that the gate voltage of NMOS can be coupled to a reasonable value.According to the PD SOI technology characteristic,GCNMOS power clamp circuits with different body bias,different implant type and different width are designed and fabricated.On the basis of transmission line pulse（TLP） measured results and analysis,gate coupled circuit composed of H gate NMOS with body floating and deep implant drain and source has the best robustness level,that is,the anti-human body model（HBM） ESD capability can be as high as 9.25 V/μm.
出处
《武汉大学学报（工学版）》
CAS
CSCD
北大核心
2011年第2期245-248,共4页
Engineering Journal of Wuhan University
基金
预先研究基金资助项目(编号:51308010610)
