摘要
为在现场可编程门阵列(FPGA)中实现快速高精度除法,在传统的倒数除法的基础上,提出一种改进算法。对倒数求解采用泰勒级数展开结合优化搜索逼近,求出各个分区间内的拟合一次两项式,再通过一次牛顿迭代提高精度。时序仿真结果表明,以该算法构建的除法器易于在FPGA上实现,时延仅为6个时钟周期,能达到2-34的有效精度和86.95 MHz的工作频率。
A new reciprocal algorithm is provided to realize the traditional reciprocal division on Field Programmable Gate Array（FPGA） with high precision and fast speed.In order to solve the reciprocal of the divisor,the Taylor series expansion is used combining with searching approximation to get a fitting binomial of degree 1 with one variable in every separated section,and the Newton-Raphson iteration is used one time to improve precision.The result of timing simulation proved that the divider based on this new division algorithm can be easily realized on FPGA.The divider can get the answer of 2-34 available accuracy only six clock pulses after input variables being given,and the highest operating frequency is 86.95 MHz.
出处
《计算机工程》
CAS
CSCD
北大核心
2011年第10期240-242,共3页
Computer Engineering
关键词
除法
现场可编程门阵列
倒数
泰勒级数
搜索逼近
牛顿迭代
division
Field Programmable Gate Array（FPGA）
reciprocal
Taylor series
searching approximation
Newton-Raphson iteration
