摘要
为了自主研发MIL-STD-1553B接口芯片,采用自顶向下的方法设计了1款专用的总线接收器IP核;使用VHDL语言书写发送器程序代码,通过FPGA平台对发送器进行了测试;结果表明,接收器的逻辑功能达到了设计要求,时序指标完全符合协议规范,实现了总线接收器的功能,具有消耗逻辑单元少的特点。
The appropriative IP core,which was used as the MIL-STD-1553B bus receiver,was designed with the top-down method.The bus receiver was programmed by VHDL language.It had been proved effective on the FPGA.The result indicated that the design which cost less logic elements of the FPGA had met the timing requirements of the bus standard.
出处
《电子测量技术》
2011年第5期68-69,76,共3页
Electronic Measurement Technology
基金
国家自然科学基金资助(60736026)
