摘要
ROHC协议是IETF专门针对无线链路的特点而设计的包头压缩规范,CRC码的产生、校验和更新是其中重要的组成部分。在分析CRC快速准确并行算法的基础上,针对ROHC中具体应用要求,给出其CRC计算的硬件并行实现设计方案,并用Verilog HDL语言编写代码进行了仿真和验证,结果表明此方案具有很好的实用性和灵活性。
ROHC protocol is a header compression standard designed by IETF,specially aiming at the characteristics of wireless link.The generation,verification,and updating of CRC codes are an important part of it.On the basis of analyzing the CRC’s quick and accurate parallel algorithm,and aiming at the specific application requirements of ROHC,the paper presents the design scheme of parallel implementation of CRC calculated hardware.Then,by using Verilog HDL language to compile codes,a module based on the method is simulated and verified.The results show that the scheme has good practicability and flexibility.
出处
《电子技术（上海）》
2011年第6期19-20,18,共3页
Electronic Technology
