摘要
随着高速数据采集系统的快速发展及其复杂性提高,其关键部分高速ADC(Analog to Digital Converter,模/数转换器)对时钟质量的要求也越来越高,为此提出了一种基于内部集成2.5 GHz VCO(压控振荡器)的低相位噪声锁相环时钟芯片AD9520[1]的高质量时钟电路设计,介绍了在5 Gs/s高速数据采集系统中AD9520的具体设计应用,包括其控制寄存器的参数配置以及初始化顺序等,给出了该高速数据采集系统的原理框图,并采用Xilinx公司ISE软件中的在线逻辑分析仪(ChipScope Pro)测试了时钟性能,实测表明整体指标达到设计要求。
As high-speed data acquisition system fast development and its complexity improved,the key part high-speed ADC requires for more stringent clock quality.For this reason,the paper introduced a high quality clock circuit design based on a low phase noise PLL chip AD9520 with integrated 2.5 GHz VCO.Introduced detail application of AD9520 in the 5 Gs/s high-speed data acquisition system,including its control registers＇ parameters configuration and initialization order etc,also proposed the block diagram of the high-speed signal acquisition system.And used the Xilinx Corporation ISE ChipScope Pro to test the clock performance,the practice proved the overall targets meet the design requirements.
出处
《电子设计工程》
2011年第16期170-173,共4页
Electronic Design Engineering
