摘要
为了满足嵌入式操作系统中实时性要求,提出了基于FPGA的中断管理方法。给出了中断管理模块的结构模型,并采用VHDL硬件描述语言将中断管理模块由硬件实现。针对中断请求和响应方式的不同特点,将其分为系统中断管理和用户中断管理,主要设计了中断源、中断嵌套和时钟节拍中断等管理的逻辑电路。通过仿真实验表明,该结构模型所采用的中断管理方法是正确的,提高了中断处理速度,可满足系统的实时性要求。
In order to fulfill the hard real-time operating system, interrupt management method be proposed based on FPGA, giving the interrupt management module structure model, and which used the VHDL hardware description language. The interrupt management method was realized based on PowerPC architecture. According to interrupt request and way of responding, interrupt management is divided into two types of system interrupt and user interrupt. In addition, interrupt source and interrupt nesting and time tick interrupt management were designed. The simulated data in the experiments had verified that the interrupt management module is designed correctly, both of which can improve system efficiency and meet the requirements of real-time operating system.
出处
《电子技术应用》
北大核心
2011年第9期49-52,共4页
Application of Electronic Technique
关键词
硬操作系统
中断管理
时钟节拍中断
FPGA
hardware operating system
interrupt manager
time tick interrupt
FPGA
