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7～11 GHz CMOS环形压控振荡器的设计 被引量：3

Design of a 7-11 GHz Ring VCO Based on CMOS Process
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摘要 设计了一种全集成差分高速环形压控振荡器(VCO)。采用三级延迟单元环路复用结构,通过正反馈技术以及改变负载电阻值的方法,有效优化延迟单元;采用双控制电压粗/细调谐方式,实现振荡器高频率、低功耗的要求。在SMIC 0.18μm CMOS RF工艺模型下,采用ADS软件对振荡电路进行仿真,在外接电源电压Vdd=1.8V时,输出频率的调谐范围为7.32～11.07GHz,当频率为11GHz时,在偏离中心频率1MHz处相位噪声为-88.32dBc/Hz,在偏离中心频率10MHz处相位噪声为-112.7dBc/Hz,平均功耗为63.5mW。该VCO可应用于锁相环和雷达通信系统。 A fully integrated differential high-speed ring voltage-controlled oscillator（VCO） was designed,which was comprised of three-stage delay cell with multi-loop structure.The delay cell was optimized by using positive feedback and modifying load resistance value.In this circuit,high frequency and low power was realized by coarse/fine frequency control.Based on SMIC＇s 0.18 μm 1P6M CMOS process model,the VCO was simulated with ADS.At 1.8 V supply voltage,the VCO had a linear tuning range from 7.32 GHz to 11.07 GHz.Simulation results showed that,for an oscillating frequency of 11 GHz,the circuit had a phase noise of-88.32 dBc/Hz and-112.7 dBc/Hz at 1 MHz and 10 MHz off center frequency,respectively,with an average power of 63.5 mW.
作者 何芝兰 段吉海
机构地区 桂林电子科技大学信息与通信学院
出处 《微电子学》 CAS CSCD 北大核心 2011年第5期664-667,共4页 Microelectronics
关键词 CMOS 压控振荡器 环路复用 相位噪声 CMOS VCO Multiloop Phase noise
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

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二级参考文献6

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共引文献18

同被引文献16

  • 1邓晶晶,李宁,李巍,陈丹凤,任俊彦.正交输出、双调谐、高性能4.488GHz环形振荡器设计[J].复旦学报（自然科学版）,2008,47(6):743-748. 被引量：1
  • 2王雪艳,朱恩,熊明珍,王志功.11GHz CMOS环形压控振荡器设计[J].Journal of Semiconductors,2005,26(1):187-191. 被引量：7
  • 3毕查德·拉扎维.模拟CMOS集成电路设计[M].西安:西安交通大学出版社,2003:337-338.
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引证文献3

二级引证文献7

微电子学
2011年 第5期

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