期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种新的VLSI功能噪声故障分析方法

A New Method for Functional Noise Failure Analysis in VLSI Design
原文传递
导出
摘要 将相邻线间的信号跳变方向考虑到噪声窗口模型中,提高计算同时跳变的干扰线在受扰线上引起的组合噪声脉冲结果的准确性;利用改进的噪声窗口模型,对受扰线的弱干扰线集合、强干扰线集合以及传播噪声同时进行分析,得到电路中精确的可实现有效噪声脉冲以及相应的有效干扰线集合。对10个MCNC基准电路进行实验,结果表明,该方法能够非常有效地滤除功能噪声分析过程中的虚假噪声故障。 Transition direction of neighboring nets was injected to noise window model,in order to improve the accuracy for computing combined noise results on victim from aggressors switching at the same time.By using the improved noise window model,insignificant/significant aggressor sets and propagated noise were analyzed simultaneously,to obtain the exact realizable effective noise glitch results and corresponding effective aggressor sets.Experimental results from 10 MCNC benchmarks showed that the proposed method could greatly reduce false noise failures in functional noise analysis.
作者 刘晓晓 吴继娟 李光顺 吴俊华
机构地区 北京城市学院电子与信息工程学部 曲阜师范大学计算机科学学院
出处 《微电子学》 CAS CSCD 北大核心 2011年第5期725-730,共6页 Microelectronics
基金 山东省优秀中青年科学家基金资助项目(BS2009DX024 BS2010DX013) 山东省高校科技计划项目(J09LG34)
关键词 VLSI 串扰噪声 功能噪声故障 噪声类 VLSI Crosstalk noise Functional noise failure Noise cluster
分类号 TP391.7 [自动化与计算机技术—计算机应用技术]
  • 相关文献

参考文献13

  • 1TAYADE G R, KALYANAM K V, NASSIF S, et al. Estimating path delay distribution considering coupling noise [C]//Proc 17th ACM Great Lakes Symp VLSI. Lago Maggiore, Italy. 2007: 61-66.
  • 2BRAJESH K, SANKAR S, RAJENDRA P A, et al. An analytical approach to dynamic erosstalk in coupled interconnects [J]. Microelec J, 2010, 41(2-3): 85-92.
  • 3MOHAMMAD M T, NASSER M. Low-power and high-performance techniques in global interconnect signaling [J]. Microelec J, 2009, 40(10): 1487-1495.
  • 4HANCHATE N, RANGANATHAN N. Integrated gate and wire sizing at post layout level [C]// IEEE Comp Soc Ann Symp VLSI. Porto Alegre, Brazil. 2007 : 225-232.
  • 5SCHEFFER L. What is the appropriate model for crosstalk control [C]// Proc 13th Symp Integr Circ Syst Des. Manaus, Brazil. 2000: 315-320.
  • 6SHEPARD K L, CHOU K. Cell characterization for noise stability [C] // Proc IEEE Cust Integr Circ Conf. Orlando, Canada. 2000: 91-94.
  • 7AJOY K P, KISHORE K D, WALTER A. Crosstalk fault modeling in defective pair of interconnects [J] VLSI J Integr, 2008, 41(1): 27-37.
  • 8LEVY R, BLAAUW D, BRACA G, et al. ClariNet: a noise analysis tool for deep submicron design [C] // Proc 37th Conf Des Autorn. Los Angeles, CA, USA. 2000 : 233-238.
  • 9TSENG K, KARIAT V. Static noise analysis with noise windows [C] // Proc 40th Conf Des Aurora. Anaheim, CA, USA. 2003: 864-868.
  • 10孙加兴,叶青,周玉梅,叶甜春.互连线间容性串扰对延迟的影响[J].固体电子学研究与进展,2005,25(3):416-421. 被引量：6

二级参考文献29

  • 1冯刚,马光胜,杜振军.动态串扰优化的开关盒布线[J].Journal of Semiconductors,2005,26(2):399-405. 被引量：4
  • 2International Technology Roadmap for Semiconductors 2002 update.
  • 3Kahng Andrew B, Muddu Sudhakar, Sarto Egino. On switch factor based analysis of coupled RC interconnects, DAC 2000:79-84.
  • 4Pileggi Lawrence. Coping with RC(L) interconnect design headaches[A]. Proceedings of the International Conference on Computer-Aided Design[C].1995:246-253.
  • 5Sapatnekar Sachin S. On the chicken-and-egg problem of determining the effect of crosstalk on delay in integrated circuits[A]. Proc IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging[C],1999:245-248.
  • 6Sapatnekar Sachin S. A timing model incorporating the effect of crosstalk on delay and its application to optimal channel routing[J]. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems,2000;19(5):550-555.
  • 7Elmore W C. The transient response of damped linear networks[J]. Journal of Applied Physics,1948;1(19):55-63.
  • 8Wyatt J L. Circuit Analysis, Simulation and Design, Elsevier Science Publishers, North-Holland,1987.
  • 9Shepard Kenneth L, Narayanan Vinod, Rose Ron. Harmony:Static noise analysis of deep submicron digital integrated circuits[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999, 18(8): 1132～1150.
  • 10Sasaki Y, de Micheli G. Crosstalk delay analysis using relative window method [A]. In: Proceedings of International ASIC/SoC Conference, Washington, D C, 1999. 9～13.

共引文献8

微电子学
2011年 第5期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部