摘要
本文以FPGA为硬件核心设计数字滤波系统,提出一种低成本高效FIR滤波器的设计方法。首先利用提出的AS型FIR滤波器实现结构,降低系统逻辑资源消耗、提高系统资源利用率及系统运行速度,然后综合采用SYSGEN和ISE实现滤波器的模块化和自动化设计,简化设计过程,降低实现难度。具体在XC3S500E4f320 FPGA上实现了一系列4阶到32阶的FIR滤波器,实验结果验证了方法的有效性。
In this paper,a cost-efficient method of designing FIR filter is proposed based on a digital filter system using FPGA as the hardware core.First of all,the proposed AS FIR filter architecture is adopted to reduce resource-consumption,increase processing speed and improve resource utilization rates of the system,and then SYSGEN and ISE are used together to implement FIR filter targeted FPGA modularly and automatically.A series of FIR filters which order from 4 to 32 are implemented targeted XC3S500E4f320 FPGA.The designed examples show that the method is very efficient.
出处
《微计算机信息》
2011年第10期62-64,95,共4页
Control & Automation
基金
基金申请人:杨红姣
项目名称:基于BJT的高阶电流模式对数域滤波器设计
基金颁发部门:湖南省教育厅(08C865)
