摘要
A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ.cm^2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.
A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ.cm^2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.
基金
supported by the National Natural Science Foundation of China(No.60906038)
the Pre-Research Foundation,China(No. 9140A08010309DZ02)
the Science-Technology Foundation for Young Scientist of University of Electronic Science and Technology of China(No.L08010301JX0830)
