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Design of A 1.2 V Low-Power Clock Generator

Design of A 1.2 V Low-Power Clock Generator
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出处 《半导体技术》 CAS CSCD 北大核心 2011年第12期953-956,共4页 Semiconductor Technology
clock generator phase-locked-loop low consumption low jitter ring oscillator.
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参考文献5

  • 1HAJIMIRI A, LEE T H. Design issues in CMOS differential LC oscillators [ J ]. IEEE J Solid-State Circuits, 1999, 34:717-724.
  • 2HAJIMIRI A, LEE T H. A general theory "of phase noise in electrical oscillators [ J ]. IEEE J Solid-State Circuits, 1998, 33: 179-194.
  • 3LEE T H. The design of CMOS radio-frequency integrated circuits [ M]. Cambridge: Cambridge University Press, 2004:566 - 595.
  • 4HUNG C M, FLOYD B A, PARK N. A fully integrated 5.35 GHz CMOS VCO and a prescaler [ J]. IEEE Trans Microwave Theory Teeh, 2001, 49 (1) : 17 -22.
  • 5RAZAVI B. Design of analog CMOS integrated circuits [M]. New York: McGraw-Hill, 2001:532 -576.

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