摘要
研究了JFET区注入对大功率VDMOS器件击穿电压和导通电阻的影响,分析讨论了JFET区注入影响击穿电压的机理,并定量给出JFET区注入对导通电阻的影响。通过器件数值模拟优化JFET区注入剂量,并根据仿真结果改进器件设计,在满足击穿电压要求的前提下导通电阻降低了8%。
Effect of ion-implanted JFET region on breakdown voltage and on-resistance of power VDMOS device was investigated.Mechanism of breakdown voltage drop induced by implantation into JFET region was discussed,and effect of implantation in JFET region on on-resistance was quantitatively analyzed.By optimizing implantation dosage with TCAD and modifying device design according to simulation results,on-resistance of the device was reduced by 8%,and breakdown voltage didn＇t drop significantly.
出处
《微电子学》
CAS
CSCD
北大核心
2011年第6期918-922,共5页
Microelectronics
基金
国家自然科学基金资助项目(60820106001)
