摘要
本文设计了时钟边沿可控双边沿触发器,在传统的双边沿触发器内部增加时钟控制电路,实现对单个时钟边沿的控制。同时,提出了基于隔态封锁技术的时序电路设计方法,可封锁时钟信号中所有冗余边沿的触发行为。HSPICE模拟与能耗分析证明,本文设计的电路不仅能够封锁所有的冗余时钟边沿的触发,而且可以简化组合电路部分的设计,从而实现更低的系统功耗。
The design of clock edge controllable dual edge-triggered flip-flop is proposed. And a novel method for low power sequential circuit design is proposed, which restraints all the redundant behaviors of the clock signal using alternate restraining technique. HSPICE simulation shows that proposed designs can simplify the circuit structure and have lower power dissipation compared to existing designs.
出处
《电路与系统学报》
CSCD
北大核心
2011年第6期13-18,共6页
Journal of Circuits and Systems
基金
国家自然科学基金资助项目(61071062)
关键词
低功耗
门控时钟
时钟边沿可控双边沿触发器
隔态封锁
low power
clock gating
clock edge controllable dual edge-triggered flip-flop
alternate restraining
