摘要
针对高速实时图像采集系统中数据量大需要缓存的问题,提出一种基于FPGA的SDRAM控制器设计方案。在分析SDRAM基本操作原理的基础上,通过引入状态机和仲裁机制,利用Verilog语言在QuartusII的开发环境中进行设计输入与仿真验证,实现了高速数据的缓存和传输。详细介绍各模块的具体设计方法以及整体设计的实现过程。实验测试结果表明:该控制器设计灵活、工作稳定可靠,成本低廉,可作为IP核应用于不同SOC的高速缓存系统中。
Aiming at the problem of large-capacity data, need memory cache in high-speed real-time image processing system, a new SDRAM controller based on FPGA was proposed. Based on the analysis of the basic operation principle of SDRAM, through introducing the state machine and arbitration mechanism, the purpose of high-speed data cache and transmission is realized by carrying on the design input and simulation validation in QuartusII development environments using Verilog language. This paper introduces the specific design of each module and the realization of the whole design in detail. The test results show that the controller designed is flexible, stable, reliable, low cost, and can be used as IP core in different SOC high-speed cache system.
出处
《兵工自动化》
2012年第2期57-60,共4页
Ordnance Industry Automation
基金
陕西省科学技术研究发展计划项目(2011K06-22)
