摘要
为了减少数字信道化接收机的硬件资源消耗,提高吞吐量,对实信号数字信道化接收机的结构进行了研究。对于实信号,提出新的信道划分方法,推导数字信道化接收机的数学模型,得到数字信道化接收机的高效结构。与一般的数字信道化接收机结构相比,该高效结构节省了硬件资源,减小了计算复杂度,提高了数字信道化接收机的吞吐量。测试结果表明,该数字信道化接收机高效结构的功能正确,性能稳定。
In order to reduce the hardware resource consumption of a digital channelized receiver and improve the throughput, the structure of the digital channelized receiver for real signals is studied. For real signals, a new channel-partition method is proposed, the mathematical model of the digital channelized receiver is derived, and an efficient structure for the digital channelized receiver is presented. Compared with the generic structure of digital channelized receivers, the efficient structure saves hardware resources, reduces the computational complexity and improves the throughput of the digital channelized receiver. The test results verify its correctness and stability.
出处
《系统工程与电子技术》
EI
CSCD
北大核心
2012年第2期391-395,共5页
Systems Engineering and Electronics
关键词
电子战
接收机
数字信道化
多相滤波
现场可编程门阵列
electronic war
receiver
digital channelization
polyphase filter
field programmable gate array
