期刊文献+

神经MOS晶体管 被引量:5

Neuron MOS Transistor
下载PDF
导出
摘要 神经MOS晶体管是1991年发明出来的一种具有高功能度的多输入栅控制的浮栅MOS器件。本文介绍了它的基本结构和特点,论述了这种新器件及其电路的国外研究现状。 The neuron MOS transistor was invented in 1991.It is a high functional floating gate MOS transistor with multiple input control gates.In this paper,the basic configuration and main characteristics of the neuron MOS transistor are introduced.The status quo and trend for the studies on this kind of new device and its integrated circuits are reviewed.The researches,which the authors have made,are also presented.
作者 管慧 汤玉生
出处 《半导体技术》 CAS CSCD 北大核心 2000年第1期2-7,共6页 Semiconductor Technology
关键词 神经MOS晶体管 浮栅器件 MOS器件 Neuron MOS transistor Floating gate device
  • 相关文献

参考文献9

  • 1[1]Shibata T,Ohmi T.IEDM Tech Digest,1991:919
  • 2[2]Shibata T,Ohmi T.IEEE Trans Electron Devices,1992;39(6):1444
  • 3[3]Ohmi T,Shibata T.IEICE Trans Electron,1997;E80-C(7):841
  • 4[4]Tsividis Y,Satyanarayana S.Electronics Letters,1987;23(24):1313
  • 5[6]Kotani K,Shibata T,Ohmi T.IEDM Tech Digest,1992:431
  • 6[7]Shibata T,Kotani K,Ohmi T.ISSCC Digest Technical papers,1993;FA 15.3:238
  • 7[8]Mehrvarz H R,Kwok C Y.IEEE J Solid-State Circuits,1996;31(8):1123
  • 8[9]K D.Solid-State Technology,1998;41(3):24
  • 9[10]Shibata T,Ohmi T.Proceedings of the IEEE Hongkong Electron Devices Meeting,1997:337

同被引文献20

  • 1汪鹏君,郁军军,戴静,黄道.钟控神经MOS管的改进及其在多值电路中的应用[J].电路与系统学报,2006,11(3):26-29. 被引量:4
  • 2杭国强,吴训威.差动电流开关的控阈技术及施密特电路[J].科技通报,1997,13(1):1-5. 被引量:2
  • 3于宗光,许居衍,魏同立.EEPROM失效机理初探[J].固体电子学研究与进展,1997,17(2):127-133. 被引量:5
  • 4荒井英辅(日) 邵春林等(译).集成电路[M].北京:科学出版社,2000.7.
  • 5Yohei Ishikawa, Sumio Fukai. A Neuron MOS variable Logic Circuit with The Simplified Circuit Structure [A]. 2004 IEEE Asia-Paclfic Conference on Advanced System Integrated Circuits [C]. Fukuoka, Japan, 2004. 436-437.
  • 6Paul Hasler, TorS Lande. Overview of Floating- gate Devices, Circuits and Systems. IEEE Transactions on Circuits and Systems. 2001, 48 (1).
  • 7Shibata T,Ohmi T.Neuron MOS Binary Logic Integrated Circuits Part Ⅰ:Design Fundamentals and Soft Hardware Logic Circuit Implementation[J].IEEE Trana.Electron Devices,1993,40:570-576.
  • 8Shibata T,Ohmi T.Neuron MOS Binary Logic Integrated Circuits Part Ⅱ:Simplifying Techniques of Circuit Configuration and Their Practical Applications[J].IEEE Trans.Electron Devices,1993,40:974-979.
  • 9Rantala A,Franssila S,Kaski K,et al.Improved Neuron MOS-transistor Structures for Integrated Neural Network Circuits[J].IEEE Proc.Circuits Syst.,2001,148:25-34.
  • 10Hui Guan,Yu Shengtang.Accurate and Efficient Models for the Simulation of Neuron MOS Integrated Circuits[J].INT Electronics,2000,87:557-568.

引证文献5

二级引证文献4

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部