摘要
关于振荡器相位噪声引起的GNSS接收机载波跟踪数字锁相环相位抖动,目前的解析结论仍是基于模拟锁相环的,不能说明相位抖动大小与中频积累时间的关系,因此不能有效指导高灵敏度、高精度载波跟踪锁相环参数设计。本文首先推导中频积累输出的频率白噪声、频率游走噪声序列的功率谱,然后基于数字二阶锁相环离散线性模型导出了环路相位抖动公式并进行了仿真验证,最后对公式进行了解析和数值分析。分析结果表明:频率白噪声、频率游走噪声引起的二阶载波跟踪锁相环相位抖动,均随中频积累时间单调递增,随环路带宽先递减后递增。本文推得的相位抖动公式及其随参数变化特征的分析结论,可用于具体指导GNSS载波跟踪锁相环参数设计。
Present analytical conclusion of GNSS carrier tracking digital phase-locked loop （DPLL） phase jitter due to oscillator phase noise is derived based on the linear model of analog PLL. It is, however, not able to reveal the relationship between phase jitter and the coherent integration time （ CIT）, and it cannot guide the high sensitivity and high precision carrier tracking DPLL parameter design effectively. Firstly, this research derived the power spectral density of white frequency and random walk frequency phase noise sequences output from the phase detector. Secondly, the formulae of phase jitter were obtained based on the DPLL linear model and verified by simulation. Finally, analytical and numerical analysis on the obtained phase jitter formulae was carried out. The analysis results show that, both of DPLL phase jitter due to white and random walk frequency noise increase as the CIT grows, and decrease firstly and then increase as the loop bandwidth grows. The phase jitter formulae and the conclusions, which describe the relationship between DPLL phase jitter and the loop bandwidth and the CIT, can be used as guideline for GNSS carrier tracking DPLL parameter design.
出处
《国防科技大学学报》
EI
CAS
CSCD
北大核心
2012年第1期127-131,共5页
Journal of National University of Defense Technology
基金
教育部新世纪人才支持计划资助项目(NCET-08-0144)
