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一种抵御侵入式分析的密码芯片存储总线 被引量:2

Security Chip Memory Bus for Resisting Invasive Analysis
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摘要 为了抵御针对密码芯片的侵入式物理分析,设计了一种片上存储安全总线.采用基于混沌映射的地址扰乱电路对存储地址进行位置置乱;同时采用存储单元加密电路对单位数据进行加密,且置乱和加密都受到密钥控制.如此,芯片内嵌存储器(如RAM、ROM、EEPROM、FLASH等)所存储的信息即便被攻击者获取也无法解读,置乱与加密的乘积效果能够有效降低了攻击者获得明文信息的概率. In order to resist invasive analysis for the crypto chip, a hardware security bus on chip is proposed to protect the data in memory. General cat-map is adopted by address generator circuit to scramble the memory address, and a memory cell encryption cir cuit is used for encrypting data unit. The scrambling and encryption are under the control of a key. In this way, even if the invasive attacker can get data in the on-chip memory( such as RAM, ROM, EEPROM and Flash ), the data still can not be understood. The product operation combined with scrambling and encrypting increases the difficulties of physical attack.
出处 《小型微型计算机系统》 CSCD 北大核心 2012年第4期785-788,共4页 Journal of Chinese Computer Systems
基金 国家发展改革委员会信息安全专项([2010]3044)资助 国家"八六三"高技术研究发展计划项目(2007AA01Z459)资助
关键词 侵入式分析 片上安全存储 密码芯片 混沌映射 invasive analysis on-chip secure storage crypto chip chaotic map
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