摘要
为了降低FPGA互连结构的功耗,针对目前FPGA普遍采用的通用互连结构,提出了快速结构评估框架—FDPAef,建立了功耗延时积的逐级优化步骤.在新型的通用开关盒互连结构(GSB)基础上,使用该评估框架对各种结构参数进行评估和优化,得到一种低功耗的GSB结构.经过MCNC基准电路测试实验表明,相比传统的CB/SB互连结构,优化得到的GSB结构能够使FPGA功耗延时积下降9.9%,面积下降10.7%.
In order to reduce the interconnect power dissipation,a fast architecture evaluation framework called FDPAef is proposed,and a proceed for optimizing the power delay product is established,for popular general interconnect architecture of FPGA.Different FPGA architectures based on the new general switch box（GSB） are evaluated and optimized with FDPAef framework,resulting in a low power architecture.The experimental MCNC benchmark result shows that compared to the common CS/BS interconnect architecture,9.9% power delay product decrease and 10.7% area decrease are achieved by this GSB interconnect architecture.
出处
《复旦学报（自然科学版）》
CAS
CSCD
北大核心
2012年第1期63-70,共8页
Journal of Fudan University：Natural Science
基金
上海市科学技术委员会基金(08706200101)资助项目
