摘要
基于FPGA硬件实现固定倍率的图像缩放,将2维卷积运算分解成2次1维卷积运算,对输入原始图像像素先进行行方向的卷积,再进行列方向的卷积,从而得到输出图像像素。把图像缩放过程设计为一个单元体的循环过程,在单元体内部,事先计算出卷积系数。降低了FPGA设计的复杂性,提高了图像缩放算法的运算速度,增强了系统的实时性,已经应用于某款航空电子产品中。
FPGA-based hardware implementation of fixed multiple image shrinking and amplifying is presented.Two-dimensional convolution is decomposed into 1-dimensional convolution twice.In order to obtain the output image pixels,the input original image pixels are convoluted in row direction,then processed pixels are convoluted in line direction.Image shrinking and amplifying process is designed to a cycle process of the unit.Inside unit,the convolution coefficients are calculated in advance.This method has been applied to a section of avionics products with good results that the complexity of FPGA design is reduced,the computing speed of image scaling algorithms is increased and the real-time of system is enhanced.
出处
《电子设计工程》
2012年第7期163-165,共3页
Electronic Design Engineering
关键词
FPGA
图像缩放
卷积运算
单元体
FPGA
image shrinking and amplifying
convolution
unit
