摘要
VHDL硬件描述语言是一种用于数字系统进行设计和测试的语言,系统硬件描述能力强,模块化和自上而下的设计思路,使得系统设计周期短、设计灵活,便于移植。通过对EDA设计方法的研究,设计采用模块化思路和VHDL语言设计实现OSI参考模型数据链路层重要协议-HDLC协议,主要设计模块有:帧同步模块、"0"比特填充与删除模块、去帧首和帧尾模块、CRC循环冗余校验生成模块等。设计能够实现利用HDLC协议的通信过程,基本功能具备。
Very High Speed IC Hardware Description Language （VHDL） is a used m digital system design and test of language, the system hardware description ability, modular and top - down design, makes the system design cycle is short, and the flexible design, for transplantation,In this article, the modular thought and VHDL language demgn realize the OSI reference model data hnk layer important agreement- in HDLC protocol , the main design module has： frame synchronization module, ＂0＂ bit filling and delete module, to frame the first and frame the tail module, CRC cyclic redundancy check generation module. Design will be able to realize the use in HDLC protocol communication, basic function have.
出处
《电气自动化》
2012年第2期16-18,共3页
Electrical Automation
